Abstract
Channel bandwidth-limited high-speed links or interfaces make circuit solutions not efficient. Both recent and subsequent links (SerDesSerializer/Deserializer) design demand efficient and effective coupling between future circuit design, communication, and optimization. The challenges vary and new solutions are needed. In this article, an analytical wireline model is presented to predict electronic path loss towards adequate designs of electronic circuits and systems. An open loop system analysis is adapted in this paper. Our model was tested against different channels: a legacy channel with via stub discontinuity and FR4 dielectric, and a more recent microwave-engineered channel without stub and NELCO 6,000 dielectric, a very good matching attained. Good agreement was observed between our model and electromagnetic full-wave simulation data, as a result showed high level of applicability to thin-film microstrip line for adequate circuit design. The model is recommended for electronic engineers for adequate and faster interfaces and high-speed links designs.
Original language | English |
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Pages (from-to) | 730-738 |
Number of pages | 9 |
Journal | Indonesian Journal of Electrical Engineering and Computer Science |
Volume | 30 |
Issue number | 2 |
DOIs | |
Publication status | Published - May 2023 |
Keywords
- Electronics
- Loss
- Microstrip channel
- Modeling
- Thin-film circuit
ASJC Scopus subject areas
- Signal Processing
- Information Systems
- Hardware and Architecture
- Computer Networks and Communications
- Control and Optimization
- Electrical and Electronic Engineering