Optimized low power hybrid adder architecture for OFDM in wireless communication

The contemporary wireless communication system makes full use of the available spectrum by making it possible to adapt to various channel situations. The extremely well-organized multi-carrier modulation technique of the orthogonal frequency division multiplexing (OFDM) transceiver design allows for faster data transmission. It is observed that the adder circuit, a power-hungry module in OFDM architectures, plays a crucial role in the multi-carrier modulation process which is a power-hungry module. Thus, this paper discusses an efficient method implementing wide word length addition by propositioning a hybrid four-bit carry generator. The carry select adder (CSA) and ripple carry adder (RCA) styles are combined and used for the proposed hybrid carry generator. It is aimed at reducing transistor counts as well as power consumption by applying RC style in the first three bits. In the fourth bit, however, the CSA method shall be applied to ensure speed. Simulation of the schematic of hybrid adder work is carried out in the tanner tool at 45nm technology and its performance in OFDM is analyzed in MATLAB. Performance parameters such as the power-delay product (PDP) of the hybrid adder concept are 41.12%with an average power consumption of 23.15% and a propagation delay of 20.21%. When additive white gaussian noise (AWGN) and rayleigh are compared in the OFDM MATLAB Model, AWGN has a better signal-to-noise ratio, with 0.0001 BER of about 18 dB across the range of modulation schemes.