Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Viranjay M. Srivastava; K. S. Yadav; G. Singh

doi:10.1016/j.proeng.2012.06.060

Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Viranjay M. Srivastava, K. S. Yadav, G. Singh

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

Independent gate control in double-gate devices enhances the circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we have explored the circuit techniques for a DP4T RF CMOS switch, which is an application of the independent double-gate MOSFET with symmetrical gate at 45-nm technology design and analyzed the better drain current, output voltage, ON resistance, ON/OFF ratio and insertion loss for the DP4T DO RF CMOS switch.

Original language	English
Pages (from-to)	486-492
Number of pages	7
Journal	Procedia Engineering
Volume	38
DOIs	https://doi.org/10.1016/j.proeng.2012.06.060
Publication status	Published - 2012
Externally published	Yes
Event	International Conference on Modelling Optimization and Computing - TamilNadu, India Duration: 10 Apr 2012 → 11 Apr 2012

Keywords

45-nm technology
CMOS
DP4T switch
Double-gate MOSFET
RF switch
Radio frcqucncy
Single-gate MOSFET
VLSI

ASJC Scopus subject areas

General Engineering

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10.1016/j.proeng.2012.06.060

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@article{fd685d6082ca4b158bc59cb91b465493,

title = "Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology",

abstract = "Independent gate control in double-gate devices enhances the circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we have explored the circuit techniques for a DP4T RF CMOS switch, which is an application of the independent double-gate MOSFET with symmetrical gate at 45-nm technology design and analyzed the better drain current, output voltage, ON resistance, ON/OFF ratio and insertion loss for the DP4T DO RF CMOS switch.",

keywords = "45-nm technology, CMOS, DP4T switch, Double-gate MOSFET, RF switch, Radio frcqucncy, Single-gate MOSFET, VLSI",

author = "Srivastava, {Viranjay M.} and Yadav, {K. S.} and G. Singh",

year = "2012",

doi = "10.1016/j.proeng.2012.06.060",

language = "English",

volume = "38",

pages = "486--492",

journal = "Procedia Engineering",

issn = "1877-7058",

publisher = "Elsevier BV",

note = "International Conference on Modelling Optimization and Computing ; Conference date: 10-04-2012 Through 11-04-2012",

}

TY - JOUR

T1 - Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

AU - Srivastava, Viranjay M.

AU - Yadav, K. S.

AU - Singh, G.

PY - 2012

Y1 - 2012

N2 - Independent gate control in double-gate devices enhances the circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we have explored the circuit techniques for a DP4T RF CMOS switch, which is an application of the independent double-gate MOSFET with symmetrical gate at 45-nm technology design and analyzed the better drain current, output voltage, ON resistance, ON/OFF ratio and insertion loss for the DP4T DO RF CMOS switch.

AB - Independent gate control in double-gate devices enhances the circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we have explored the circuit techniques for a DP4T RF CMOS switch, which is an application of the independent double-gate MOSFET with symmetrical gate at 45-nm technology design and analyzed the better drain current, output voltage, ON resistance, ON/OFF ratio and insertion loss for the DP4T DO RF CMOS switch.

KW - 45-nm technology

KW - CMOS

KW - DP4T switch

KW - Double-gate MOSFET

KW - RF switch

KW - Radio frcqucncy

KW - Single-gate MOSFET

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=84874882282&partnerID=8YFLogxK

U2 - 10.1016/j.proeng.2012.06.060

DO - 10.1016/j.proeng.2012.06.060

M3 - Conference article

AN - SCOPUS:84874882282

SN - 1877-7058

VL - 38

SP - 486

EP - 492

JO - Procedia Engineering

JF - Procedia Engineering

T2 - International Conference on Modelling Optimization and Computing

Y2 - 10 April 2012 through 11 April 2012

ER -

Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology

Abstract

Keywords

ASJC Scopus subject areas

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