Experimentation of Bandpass NGD Inductorless Integrated Circuit Designed with 180-nm CMOS Technology RC-Network

Miniaturization remains a critical challenge for Negative Group Delay (NGD) circuit design. This paper presents an inductorless bandpass (BP) NGD integrated circuit (IC) designed based on an RC-topology leveraging 180-nm complementary metal-oxide-semiconductor (CMOS) technology. The schematic and layout of the BP-NGD CMOS IC prototype are designed with CADENCE VIRTUOSO® commercial tool. The compact BP-NGD chip area is 1.06 mm × 0.55 mm. The key performance metrics include a center frequency of 18.67 MHz, an NGD of -0.91 ns, a bandwidth of 74.31 MHz, a maximum insertion loss of -3.86 dB, and a minimum return loss of -11.04 dB. The results demonstrate that the IC design effectively balances miniaturization with high-performance NGD characteristics, providing a promising solution for NGD integration in system-on-chip (SoC) applications.