Design of an integrated CMOS PLL frequency synthesizer

Keyphrases

• Wireless Transceiver 100%
• Synthesizer 100%
• Integrated CMOS 100%
• Phase-locked Loop 100%
• Frequency Synthesizer 100%
• High Cost 50%
• Power Consumption 50%
• Bulkiness 50%
• Sidebands 50%
• GHz Range 50%
• Phase Noise 50%
• Post-layout Simulation 50%
• CMOS Process 50%
• Discrete Element Method 50%
• Loop Architecture 50%
• Large Power 50%
• Dual Phase-locked Loop 50%

Engineering

• Transceiver 100%
• Phase Locked Loop 100%
• Electric Power Utilization 50%
• Phase Noise 50%
• Discrete Element 50%
• Sidebands 50%