Abstract
Due to higher costs, bulkiness and larger power consumption, it is no longer desirable to implement wireless transceivers with discrete elements. This paper describes the design of an essential component in wireless transceivers, the frequency synthesizer. The synthesizer is implemented using the dual phase locked loop (PLL) architecture. The synthesizer generates signals in the 2.4-2.5 GHz range with a 1 MHz resolution. Using the 0.35 μm CMOS process, post-layout simulations showed a phase noise of -82 dBc/Hz at an offset of 10 kHz and reference sidebands at -60 dBc, both these parameters with respect to a 2.45 GHz carrier.
| Original language | English |
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| Pages | 220-224 |
| Number of pages | 5 |
| Publication status | Published - 2002 |
| Externally published | Yes |
| Event | 11th IEEE Mediterranean Electronical Conference (Melecon 2002) - Cairo, Egypt Duration: 7 May 2002 → 9 May 2002 |
Conference
| Conference | 11th IEEE Mediterranean Electronical Conference (Melecon 2002) |
|---|---|
| Country/Territory | Egypt |
| City | Cairo |
| Period | 7/05/02 → 9/05/02 |
Keywords
- On-chip inductor
- Phase locked loop (PLL)
- Single sideband (SSB) mixer
- Voltage controlled oscillator (VCO)
ASJC Scopus subject areas
- Electrical and Electronic Engineering