Abstract
Due to higher costs, bulkiness and larger power consumption, it is no longer desirable to implement wireless transceivers with discrete elements. This paper describes the design of an essential component in wireless transceivers, the frequency synthesizer. The synthesizer is implemented using the dual phase locked loop (PLL) architecture. The synthesizer generates signals in the 2.4-2.5 GHz range with a 1 MHz resolution. Using the 0.35 μm CMOS process, post-layout simulations showed a phase noise of -82 dBc/Hz at an offset of 10 kHz and reference sidebands at -60 dBc, both these parameters with respect to a 2.45 GHz carrier.
| Original language | English |
|---|---|
| Pages | 525-529 |
| Number of pages | 5 |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | 2004 IEEE AFRICON: 7th AFRICON Conference in Africa: Technology Innovation - Gaborone, Botswana Duration: 15 Sept 2004 → 17 Sept 2004 |
Conference
| Conference | 2004 IEEE AFRICON: 7th AFRICON Conference in Africa: Technology Innovation |
|---|---|
| Country/Territory | Botswana |
| City | Gaborone |
| Period | 15/09/04 → 17/09/04 |
Keywords
- On-chip inductor
- Phase locked loop (PLL)
- Single sideband (SSB) mixer
- Voltage controlled oscillator (VCO)
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering