Design methodology for a CMOS based power amplifier deploying a passive inductor

M. Božanić, S. Sinha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)


This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 μm single-supply process for a 10 dBm, 2.4 GHz PA design.

Original languageEnglish
Title of host publicationIEEE AFRICON 2007
Publication statusPublished - 2007
Externally publishedYes
EventIEEE AFRICON 2007 - Windhoek, South Africa
Duration: 26 Sept 200728 Sept 2007

Publication series

NameIEEE AFRICON Conference


ConferenceIEEE AFRICON 2007
Country/TerritorySouth Africa


  • Class-E amplifier
  • Impedance matching
  • Power amplifier
  • SPICE netlist
  • Spiral inductor

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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