Design and implementation of a fractional-n frequency synthesizer for cellular systems

P. J. Venter; S. Sinha

Design and implementation of a fractional-n frequency synthesizer for cellular systems

P. J. Venter, S. Sinha

University of Pretoria

Research output: Contribution to journal › Article › peer-review

Abstract

Frequency synthesis presents one of the most challenging subsystems in a monolithic transceiver implementation. This paper presents a PLL (phase-locked loop) frequency synthesizer based on fractional-N frequency synthesis techniques, employing direct charge injection for fractional spurious tone reduction and an integrated VCO (voltage-controlled oscillator) with an active inductor resonant tank. A 0.35 μm CMOS process is used for implementation.

Original language	English
Pages (from-to)	93-99
Number of pages	7
Journal	Transactions of the South African Institute of Electrical Engineers
Volume	97
Issue number	1
Publication status	Published - Mar 2006
Externally published	Yes

Keywords

Active inductor VCO
Current mode DAC
Fractional-n
Frequency synthesis

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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abstract = "Frequency synthesis presents one of the most challenging subsystems in a monolithic transceiver implementation. This paper presents a PLL (phase-locked loop) frequency synthesizer based on fractional-N frequency synthesis techniques, employing direct charge injection for fractional spurious tone reduction and an integrated VCO (voltage-controlled oscillator) with an active inductor resonant tank. A 0.35 μm CMOS process is used for implementation.",

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AB - Frequency synthesis presents one of the most challenging subsystems in a monolithic transceiver implementation. This paper presents a PLL (phase-locked loop) frequency synthesizer based on fractional-N frequency synthesis techniques, employing direct charge injection for fractional spurious tone reduction and an integrated VCO (voltage-controlled oscillator) with an active inductor resonant tank. A 0.35 μm CMOS process is used for implementation.

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KW - Current mode DAC

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KW - Frequency synthesis

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Design and implementation of a fractional-n frequency synthesizer for cellular systems

Abstract

Keywords

ASJC Scopus subject areas

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