TY - JOUR
T1 - Design and analysis of a single source seven level common ground SC based multilevel inverter topology with high reliability
AU - Hussain, Md Tahmid
AU - Sarwar, Adil
AU - Hussan, Md Reyaz
AU - Tariq, Mohd
AU - Ahmad, Shafiq
AU - Bakhsh, Farhad Ilahi
AU - Zaid, Mohammad
AU - Mohamed, Adamali Shah Noor
AU - Khan, Baseem
N1 - Publisher Copyright:
© The Author(s) 2025.
PY - 2025/12
Y1 - 2025/12
N2 - A switched-capacitor (SC)-based, single-stage, seven-level (7 L) inverter with a common ground is proposed to address the need for efficient and reliable power conversion in modern applications. Existing multilevel inverter (MLI) topologies often suffer from high voltage stress, increased THD, and complex control requirements. This study aims to design a compact inverter with improved performance metrics, including efficiency, total harmonic distortion (THD), and voltage stress. The proposed inverter employs a single DC source, 8 switches, 2 diodes, and 3 capacitors, achieving a threefold voltage boost without requiring additional control for self-balancing capacitor voltages. Nearest level pulse width modulation (PWM) is used to generate switching pulses, while reliability analysis ensures a robust system under short-circuit and open-circuit faults. Efficiency and power losses are evaluated using PLECS thermal modeling, and SC selection criteria are discussed to enhance performance. Results indicate that the proposed inverter achieves an efficiency of 97.4% for a 600 W load, reduced leakage current, improvements in THD, minimized conduction loss, and high-power density. To verify the suggested inverter performance, a valid thorough comparison of other recent CGSC-7 L topologies and MLIs with the suggested topology has been provided. Experimental validations under various loading and modulation conditions confirm the simulation outcomes, showcasing the inverter’s robust and dynamic performance.
AB - A switched-capacitor (SC)-based, single-stage, seven-level (7 L) inverter with a common ground is proposed to address the need for efficient and reliable power conversion in modern applications. Existing multilevel inverter (MLI) topologies often suffer from high voltage stress, increased THD, and complex control requirements. This study aims to design a compact inverter with improved performance metrics, including efficiency, total harmonic distortion (THD), and voltage stress. The proposed inverter employs a single DC source, 8 switches, 2 diodes, and 3 capacitors, achieving a threefold voltage boost without requiring additional control for self-balancing capacitor voltages. Nearest level pulse width modulation (PWM) is used to generate switching pulses, while reliability analysis ensures a robust system under short-circuit and open-circuit faults. Efficiency and power losses are evaluated using PLECS thermal modeling, and SC selection criteria are discussed to enhance performance. Results indicate that the proposed inverter achieves an efficiency of 97.4% for a 600 W load, reduced leakage current, improvements in THD, minimized conduction loss, and high-power density. To verify the suggested inverter performance, a valid thorough comparison of other recent CGSC-7 L topologies and MLIs with the suggested topology has been provided. Experimental validations under various loading and modulation conditions confirm the simulation outcomes, showcasing the inverter’s robust and dynamic performance.
KW - 7-Level inverter
KW - Common-ground
KW - Multilevel inverter
KW - Reduced component
KW - Reliability
KW - Switched-capacitor
UR - https://www.scopus.com/pages/publications/105011852598
U2 - 10.1038/s41598-025-95107-6
DO - 10.1038/s41598-025-95107-6
M3 - Article
C2 - 40717208
AN - SCOPUS:105011852598
SN - 2045-2322
VL - 15
JO - Scientific Reports
JF - Scientific Reports
IS - 1
M1 - 27348
ER -