COMMUNICATIONS TECHNIQUES IN FAULT TOLERANT ARRAYS OF MICROPROCESSORS.

D. C. Rogerson; J. R. Armstrong; F. G. Gray

COMMUNICATIONS TECHNIQUES IN FAULT TOLERANT ARRAYS OF MICROPROCESSORS.

D. C. Rogerson, J. R. Armstrong, F. G. Gray

School of Tourism and Hospitality

Research output: Contribution to conference › Paper › peer-review

Abstract

The motivation for the development of a computing system which is implemented as a large array of microprocessors is discussed. It is determined that the system should be fault tolerant and that the interconnection network of the array is of primary importance. Several interconnection techniques for large fault tolerant arrays of microprocessors are examined.

Original language	English
Pages	208-211
Number of pages	4
Publication status	Published - 1979
Event	Proc SOUTHEASTCON Reg 3 Conf - Roanoake, VA, USA Duration: 1 Apr 1979 → 4 Apr 1979

Conference

Conference	Proc SOUTHEASTCON Reg 3 Conf
City	Roanoake, VA, USA
Period	1/04/79 → 4/04/79

ASJC Scopus subject areas

General Engineering

Cite this

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title = "COMMUNICATIONS TECHNIQUES IN FAULT TOLERANT ARRAYS OF MICROPROCESSORS.",

abstract = "The motivation for the development of a computing system which is implemented as a large array of microprocessors is discussed. It is determined that the system should be fault tolerant and that the interconnection network of the array is of primary importance. Several interconnection techniques for large fault tolerant arrays of microprocessors are examined.",

author = "Rogerson, {D. C.} and Armstrong, {J. R.} and Gray, {F. G.}",

year = "1979",

language = "English",

pages = "208--211",

note = "Proc SOUTHEASTCON Reg 3 Conf ; Conference date: 01-04-1979 Through 04-04-1979",

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TY - CONF

T1 - COMMUNICATIONS TECHNIQUES IN FAULT TOLERANT ARRAYS OF MICROPROCESSORS.

AU - Rogerson, D. C.

AU - Armstrong, J. R.

AU - Gray, F. G.

PY - 1979

Y1 - 1979

N2 - The motivation for the development of a computing system which is implemented as a large array of microprocessors is discussed. It is determined that the system should be fault tolerant and that the interconnection network of the array is of primary importance. Several interconnection techniques for large fault tolerant arrays of microprocessors are examined.

AB - The motivation for the development of a computing system which is implemented as a large array of microprocessors is discussed. It is determined that the system should be fault tolerant and that the interconnection network of the array is of primary importance. Several interconnection techniques for large fault tolerant arrays of microprocessors are examined.

UR - http://www.scopus.com/inward/record.url?scp=0018310391&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0018310391

SP - 208

EP - 211

T2 - Proc SOUTHEASTCON Reg 3 Conf

Y2 - 1 April 1979 through 4 April 1979

ER -

COMMUNICATIONS TECHNIQUES IN FAULT TOLERANT ARRAYS OF MICROPROCESSORS.

Abstract

Conference

ASJC Scopus subject areas

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Cite this