CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system

Neil Naudé; Louis P. Linde; Saurabh Sinha

doi:10.1109/AFRCON.2007.4401590

CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system

Neil Naudé, Louis P. Linde, Saurabh Sinha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 ?m CMOS process from Austria Microsystems (AMS).

Original language	English
Title of host publication	IEEE AFRICON 2007
DOIs	https://doi.org/10.1109/AFRCON.2007.4401590
Publication status	Published - 2007
Externally published	Yes
Event	IEEE AFRICON 2007 - Windhoek, South Africa Duration: 26 Sept 2007 → 28 Sept 2007

Publication series

Name	IEEE AFRICON Conference

Conference

Conference	IEEE AFRICON 2007
Country/Territory	South Africa
City	Windhoek
Period	26/09/07 → 28/09/07

Keywords

Code division multiple access
Cross coupled devices
Receiver
Synchronization
Tracking loops
Voltage controlled oscillator

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/AFRCON.2007.4401590

Cite this

@inproceedings{9f89af6be1344b2ebc421925d03c0524,

title = "CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system",

abstract = "For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 ?m CMOS process from Austria Microsystems (AMS).",

keywords = "Code division multiple access, Cross coupled devices, Receiver, Synchronization, Tracking loops, Voltage controlled oscillator",

author = "Neil Naud{\'e} and Linde, {Louis P.} and Saurabh Sinha",

year = "2007",

doi = "10.1109/AFRCON.2007.4401590",

language = "English",

isbn = "142440987X",

series = "IEEE AFRICON Conference",

booktitle = "IEEE AFRICON 2007",

note = "IEEE AFRICON 2007 ; Conference date: 26-09-2007 Through 28-09-2007",

}

TY - GEN

T1 - CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system

AU - Naudé, Neil

AU - Linde, Louis P.

AU - Sinha, Saurabh

PY - 2007

Y1 - 2007

N2 - For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 ?m CMOS process from Austria Microsystems (AMS).

AB - For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 ?m CMOS process from Austria Microsystems (AMS).

KW - Code division multiple access

KW - Cross coupled devices

KW - Receiver

KW - Synchronization

KW - Tracking loops

KW - Voltage controlled oscillator

UR - http://www.scopus.com/inward/record.url?scp=48649083617&partnerID=8YFLogxK

U2 - 10.1109/AFRCON.2007.4401590

DO - 10.1109/AFRCON.2007.4401590

M3 - Conference contribution

AN - SCOPUS:48649083617

SN - 142440987X

SN - 9781424409877

T3 - IEEE AFRICON Conference

BT - IEEE AFRICON 2007

T2 - IEEE AFRICON 2007

Y2 - 26 September 2007 through 28 September 2007

ER -

CMOS based Decision Directed Costas Carrier Recovery Loop (DDC-CRL) for a DSSS communication system

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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