Bandpass Type Negative Group Delay Design of CMOS RC-Network Integrated Circuit

Nowadays, microelectronic integrated circuit (IC) design constitutes the biggest challenge of negative group delay (NGD) electronic engineering research. Bandpass (BP) type NGD circuits are generally designed with resonant and not-integrable inductive large size network-based topology. However, BP-NGD circuit integrability is delimited by the inductor design. A design solution for fully resistive-capacitive (RC) network-based BP-type IC in 130-nm CMOS technology is the purpose of the present research work. The theory expressing the design equations of RC-network based BP-NGD circuit is developed. The design feasibility is verified with a proof-of-concept (POC) represented by a 130-nm CMOS RC-network passive IC with 0.68 mm× 0.72 mm physical size simulated by Cadence®. The obtained results of S-parameters confirm the BP-NGD behavior of the CMOS IC POC with 21.9-MHz NGD center frequency and −0.99-ns NGD value over 68-MHz NGD bandwidth. The BP-NGD characterization results are in excellent agreement with the theoretical model. The robustness of 130-nm CMOS BP-NGD RC passive IC is explored by 2000 trials Monte Carlo statistical analysis with respect to the uncertainty of component parameters.