Analysis of drain current and switching speed for SPDT switch and DPDT switch with the proposed DP4T RF CMOS switch

Conventional CMOS switch uses NMOS as transistors in its main architecture requiring a control voltage of 5.0 V and a large resistance at the receivers and antennas (ANTs) to detect the signal. A CMOS integrated circuit switch uses FET transistors to achieve switching between multiple paths, because of its high value of control voltage. Hence it is not suitable for modern portable devices which demand lesser power consumption. Therefore, we proposed a new Double-Pole Four-Throw (DP4T) switch by using RF CMOS technology and analyzed its performance. Further, main objective is to provide a plurality of such switches arranged in a densely configured switch array, where the power and area could be reduced as compared to already existing switch configuration as SPDT and Double-Pole Double-Throw (DPDT) transceiver switches, which is simply a reduction of signal strength during transmission of the RF signals. The presented result for the proposed DP4T switch reveals the peak output currents (drain current) around 0.116-0.387 mA and a switching speed of 19-36 ps.