Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences

Tinu Sabu Elenjical; Louis Linde; Saurabh Sinha

doi:10.1109/MELCON.2008.4618464

Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences

Tinu Sabu Elenjical, Louis Linde, Saurabh Sinha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delaylock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 μm complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.

Original language	English
Title of host publication	MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference
Pages	380-386
Number of pages	7
DOIs	https://doi.org/10.1109/MELCON.2008.4618464
Publication status	Published - 2008
Externally published	Yes
Event	MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference - Ajaccio, France Duration: 5 May 2008 → 7 May 2008

Publication series

Name	Proceedings of the Mediterranean Electrotechnical Conference - MELECON

Conference

Conference	MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference
Country/Territory	France
City	Ajaccio
Period	5/05/08 → 7/05/08

Keywords

Analogue complex delay-lock loop
Analogue decision directed coherent Costas recovery loop
Complex spreading sequences
Pseudonoise coded communication

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/MELCON.2008.4618464

Cite this

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title = "Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences",

abstract = "A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delaylock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 μm complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.",

keywords = "Analogue complex delay-lock loop, Analogue decision directed coherent Costas recovery loop, Complex spreading sequences, Pseudonoise coded communication",

author = "Elenjical, {Tinu Sabu} and Louis Linde and Saurabh Sinha",

year = "2008",

doi = "10.1109/MELCON.2008.4618464",

language = "English",

isbn = "9781424416332",

series = "Proceedings of the Mediterranean Electrotechnical Conference - MELECON",

pages = "380--386",

booktitle = "MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference",

note = "MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference ; Conference date: 05-05-2008 Through 07-05-2008",

}

Elenjical, TS, Linde, L & Sinha, S 2008, Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences. in MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference., 4618464, Proceedings of the Mediterranean Electrotechnical Conference - MELECON, pp. 380-386, MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference, Ajaccio, France, 5/05/08. https://doi.org/10.1109/MELCON.2008.4618464

Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences. / Elenjical, Tinu Sabu; Linde, Louis; Sinha, Saurabh.
MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference. 2008. p. 380-386 4618464 (Proceedings of the Mediterranean Electrotechnical Conference - MELECON).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Linde, Louis

AU - Sinha, Saurabh

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N2 - A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delaylock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 μm complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.

AB - A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delaylock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 μm complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.

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Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences

Abstract

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Keywords

ASJC Scopus subject areas

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