A pipeline analogue to digital converter in 0.35 μm CMOS

S. W. Ross, S. Sinha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper describes an 8-bit, 130 MS/s pipelined analogue to digital converter (ADC) implemented in 0.35 μm CMOS technology from Austria Microsystems (AMS). The specifications for the design presented in this paper are in terms sampling frequency, power consumption, integral non-linearity (INL), differential non-linearity (DNL), signal to noise and distortion ratio (SNDR), and signal to quantization noise ratio (SQNR). The design achieved a SNDR of 47 dB corresponding to an effective number of bits (ENOB) of 7.5 bits. The system was designed to operate with a front-end working according to the Digital European Cordless Telecommunications (DECT) standard.

Original languageEnglish
Title of host publicationEUROCON 2007 - The International Conference on Computer as a Tool
Pages1096-1100
Number of pages5
DOIs
Publication statusPublished - 2007
Externally publishedYes
EventEUROCON 2007 - The International Conference on Computer as a Tool - Warsaw, Poland
Duration: 9 Sept 200712 Sept 2007

Publication series

NameEUROCON 2007 - The International Conference on Computer as a Tool

Conference

ConferenceEUROCON 2007 - The International Conference on Computer as a Tool
Country/TerritoryPoland
CityWarsaw
Period9/09/0712/09/07

Keywords

  • Dynamic comparator
  • Pipeline analogue to digital converter
  • Sample and hold

ASJC Scopus subject areas

  • General Computer Science
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A pipeline analogue to digital converter in 0.35 μm CMOS'. Together they form a unique fingerprint.

Cite this